The approaches described in this section are approaches that could be pursued, but not necessarily approaches that have been previously conceived or pursued. Therefore, unless otherwise indicated, it should not be assumed that any of the approaches described in this section qualify as prior art merely by virtue of their inclusion in this section.
Field programmable gate array (FPGA) integrated circuits are semiconductor devices having a matrix of configurable logic blocks (CLBs) that can be configured to produce different complex digital circuits. The CLBs are connected via programmable interconnects that span the area of the FPGA. FPGAs also may include random-access memory, digital signal processor (DSP) slices, or other logical elements. CLBs can be configured to produce logical operations such as AND and XOR, which are then coupled in series and/or parallel with other logical elements on the FPGA to produce a specified digital circuit.
FPGA configurations are described using a hardware description language (HDL) such as Verilog or VHDL. Programs written in an HDL are compiled using specialized software to generate bitstreams that contain configuration information for a particular target FPGA. VIVADO is an example integrated design environment that can be used to write and compile HDL designs to generate bitstreams for Xilinx FPGAs.
FPGAs have proven extremely powerful for implementing high-speed DSP or highly parallel DSP algorithms. FPGAs are commercially available from Xilinx, Inc., for example. FPGAs have enabled the creation of reconfigurable digital electronic products. One example is Moku:Lab, developed by Liquid Instruments Pty Ltd. However, present techniques for programming FPGAs suffer from several drawbacks.
Programming FPGAs typically requires specialized knowledge that can be time-consuming to learn. Often compilation tools are only available from the maker or vendor of the FPGA and have interfaces that are unique to those chips. Users must invest time in installing these tools as well as learning them. Development times can be long, depending on complexity. Furthermore, the time to compile a completed program, including for design changes or throughout development, can be on the order of several minutes to many hours, depending on complexity. Today's developers, faced with making a relatively simple change to an FPGA program, do not want to wait hours for the entire bitstream to be recompiled and delivered prior to loading into the FPGA.
Based on these issues, improved techniques for FPGA programming are needed and there is a specific long-felt but unfulfilled need for a way to greatly shorten the time to compile FPGA programs.